a) Field of the Invention
The present invention relates to measurement of a semiconductor manufacture process, and more particularly to the measurement of electron shading damage caused during a semiconductor manufacture process which uses plasma.
In this specification, "electron shading damage" means the damage caused by excessive positive charges injected into a surface of a conductive material layer because electrons are shaded from injecting into the surface.
b) Description of the Related Art
High integration (miniaturized patterns of constituent elements) and large diameter of semiconductor wafers are becoming usual in the manufacture of semiconductor integrated circuit devices. To meet these technical advancements, low pressure and high density plasma is now essential to ultrafine patterning techniques. In a plasma process, the amounts of positive and negative charges in plasma are controlled to be balanced in order not to be influenced by charges injected from the plasma into a semiconductor substrate.
However, even if a plasma which has a uniform charge distribution on a flat surface is used, it is reported that charging damages, characteristic to high density plasma, called electron shading damages, may occur during a plasma process if a resist mask having an opening of a high aspect ratio is used.
The electron shading damages have been considered as resulting from a difference in motion between electrons and ions. A bias potential is generally applied between a semiconductor substrate and a plasma so that ions having positive charges are accelerated and become incident upon the substrate. On the other hand, electrons having negative charges are decelerated by the bias electric field. As a result, while ions are incident upon the substrate generally vertically, electrons are incident obliquely because of relatively increased velocity components in the directions parallel to the substrate surface.
If an insulating material pattern is formed on the surface of a conductive material layer to be processed, obliquely incident electrons are shaded by this insulating material pattern. However, vertically incident ions are not shaded by the insulating material pattern and reach the conductive material surface. From this reason, excessive positive charges flow into the surface of the conductive material layer.
When electrons are captured on the side walls of the insulating material pattern, an electric field which is directed to repulse incident electrons is generated. Most of electrons having a small kinetic energy in the vertical direction are repulsed by this electric field. This is presumably the reason for occurrence of electron shading.
Since ions having positive charges are rather attracted by this electric field, they are forced to further progress into the conductive material surface layer under the insulating material pattern. If a conductive layer under the insulating material pattern is electrically isolated, positive charges are accumulated on this conductive layer. If the conductive layer is connected to an insulated gate electrode, an electric field is applied to the gate insulating film. As accumulated charges increase, the electric field becomes strong, if this electric field allows tunneling current to flow through the gate insulating film, the accumulated charges reduce and the electric field weakens. The positive charges accumulated on the conductive layer will therefore take a steady state. The gate insulating film may be deteriorated by this tunneling current.
If the gate insulating film is thick, tunneling current is hard to flow. As the amount of positive charges accumulated on the conductive layer increases, an electric field directed to attract electrons to the surface becomes strong. As electrons are attracted by this electric field, the steady state may be recovered without a presence of tunneling current.
However, gate insulating films are becoming thinner as MOS transistors are made finer. With a thin gate insulating film, tunneling current becomes easy to flow by electron shading and the lifetime of gate insulating films is shortened.
In order to improve the reliability of semiconductor devices manufactured through a low pressure and high density plasma process, it is essential to measure the degree of charging damages caused by electron shading (electron shading damages).
One known method of measuring electron shading damages is to connect a comb-shaped antenna to the gate electrode of a MOS transistor and measure a threshold voltage shift caused during a plasma process on the comb-shaped antenna.
Tunnel current flowing through the gate oxide film by electron shading damages shifts the threshold voltage of a MOS transistor. By measuring the shifted threshold voltage, the amount of charges flowed through the gate oxide film can be estimated.
This method requires a specific MOS transistor used for the measurement of electron shading damages. Various process parameters are required to be optimized before performing manufacture processes. In such a case, to manufacture samples with MOS transistor structures dedicated only to monitoring the process conditions raises cost.
For more simplified measurement samples, MOS capacitors (only gate electrodes) may be used without forming MOS transistor structures. In this case, although threshold voltages cannot be measured, breakdown voltages of insulating films of MOS capacitors are measured. However, a precision of measuring dielectric breakdown voltages of MOS capacitors is not so high that charging damages are quantified to a required precision degree.
As described above, although the degree of electron shading damages can be quantitatively measured by using MOS transistor test samples and monitoring processes, cost is raised by the manufacture of such test samples. If MOS capacitor test samples are used, however, the measurement precision becomes low although the cost can be reduced.